1. Field of the Invention
The present invention relates to a start-up circuit built in a voltage supply circuit, for example, a band gap reference voltage circuit, and operating at the time of start-up of the band gap reference voltage circuit so as to make the reference voltage circuit start up more reliably and to a voltage supply circuit constituted using the same.
2. Description of the Related Art
In the past, in a band gap reference voltage circuit utilizing feedback of an operational amplifier circuit (hereinafter simply referred to as an "operational amplifier") or other circuit which does not start operating normally until some sort of signal is given in the feedback loop of the operational amplifier at the time of start-up of the circuit, a start-up circuit which is simple in configuration and able to make the circuit start up reliably has been considered necessary.
FIG. 1 is a circuit diagram of an example of a voltage supply circuit including a start-up circuit of the related art.
As illustrated, the voltage supply circuit of this related art is constituted by a start-up circuit 10 and a band gap reference voltage circuit 20. The start-up circuit 10 is constituted by an inverter INV101, a NAND gate NA101, and a delay circuit D101. Note that pMOS transistors T104, T105 and an inverter INV102 also contribute to the operation of the band gap reference voltage circuit 20, so the circuit formed by these circuit elements is also considered as a constituent part of the start-up circuit.
When receiving a standby signal STB, the start-up circuit 10 generates signals S1 and S2 for making the band gap reference voltage circuit 20 operate reliably in response to the standby signal STB.
The band gap reference voltage circuit 20 is constituted by an operational amplifier OPA1, pMOS transistors T101, T102, and T103, and diode-connected npn transistors B101, B102, and B013.
The transistor T101, the resistor R101, and the diode-connected transistor B101 are connected in series between the supply line of the power supply voltage V.sub.CC and a reference potential, for example, the supply line of the ground potential GND, the transistor T102 and the diode-connected transistor B102 are connected in series between the supply line of the power supply voltage V.sub.CC and the ground potential GND, and the transistor T103, the resistor R102, and the diode-connected transistor B103 are connected in series between the supply line of the power supply voltage V.sub.CC and the ground potential GND. The transistors T101, T102, and T103 are together connected at their gates to an output terminal of the operational amplifier OPA1 and output currents I1, I2, and I3 in accordance with an output signal of the operational amplifier OPA1.
The positive input terminal (+) of the operational amplifier OPA1 is connected to a node n1 between the transistor T101 and the resistor R101, while the negative input terminal (-) is connected to a node n2 between the transistor T102 and transistor B102. The output signal of the operational amplifier OPA1 is supplied to the gates of the transistors T101, T102, and T103. For this reason, a feedback loop is formed by the operational amplifier OPA1. By the control of the feedback loop, during normal operation, the currents I1, I2, and I3 of the transistors T101, T102, and T103 are controlled so that the voltages of the nodes n1 and n2 become equal.
In the standby (idle) state, the output terminal of the operational amplifier OPA1, that is, the node n3, is kept in a high impedance state. During this time, since the standby signal STB is at a high level, the output terminal of the inverter INV102 is held at a low level and the transistor T105 turns on, so the node n3 is held substantially at the level of the power supply voltage V.sub.CC. Consequently, since the transistors T101, T102, and T103 turn off and no DC current flows, the voltages of the nodes n1 and n2 are not stable. When starting operation, as the standby signal STB switches from the high level to the low level, the output terminal of the inverter INV102 switches from the low level to the high level, so the transistor T105 turns off and the operational amplifier OPA1 controls the voltage of the node n3 in accordance with the input voltages of the nodes n1 and n2. Accordingly, the currents I1, I2, and I3 of the transistors T101, T102, and T103 are controlled.
If there were no start-up circuit and the voltage of the node n1 were higher than the voltage of the node n2, that is, V.sub.n1 &gt;V.sub.n2, the operational amplifier OPA1 would continuously output a signal of the high level since the voltage input to the positive input terminal (+) is higher than the voltage supplied to the negative input terminal (-). In such a situation, the band gap reference voltage circuit 20 cannot operate normally.
As described above, the standby signal STB is held at the high level when the voltage supply circuit is idling and is switched from the high level to the low level when the voltage supply circuit starts operating. Accordingly, the illustrated start-up circuit 10 outputs a signal S1 at a low level from the trailing edge of the standby signal STB during the delay time .DELTA.td of the delay circuit D101. At other times, the standby signal STB is held at the high level.
While the signal S1 is at the low level, the transistor T104 is on, so the current flowing through the transistor T104 is input to the node n2. The emitter area of the diode-connected transistor B101 is made larger than the emitter area of the transistor B102. For this reason, when the same currents flow through these transistors or a current only flows through the transistor B102, the voltage V.sub.n2 of the node n2 always becomes higher than the voltage V.sub.n1 of the node n1 at the beginning of the operation. As a result, in the operational amplifier OPA1, the voltage input to the negative input terminal (-) is higher than that input to the positive input terminal (+) and the output signal is held at the low level. According to this, the transistors T101, T102, and T103 turn on, and the currents I1, I2, and I3 are output.
The signal S1 input to the gate of the transistor T104 is held at the low level for exactly the time set by the delay time .DELTA.td of the delay circuit D101, then is switched to the high level. Since the transistor T104 is on for exactly the period when the signal S1 is at the low level and then turns off, the band gap reference voltage circuit 20 is controlled by the feedback loop formed by the operational amplifier OPA1, and a stable voltage V.sub.OUT is output from the output terminal T.sub.OUT free from any dependency on the power supply voltage V.sub.CC and temperature.
Summarizing the problem to be solved by the invention, in the voltage supply circuit of the related art described above, due to the control by the start-up circuit 10 after start-up so as to turn off the transistor T105 and to turn on the transistor T104 for exactly a certain constant time and then turn it off, normal start-up becomes possible regardless of the voltages of the node n1 and n2 while idle. Here, if the transistor T014 is held in the on state, since the feedback loop formed by the operational amplifier OPA1 cannot operate normally and the operational amplifier OPA1 cannot control the transistors T101, T102, and T103, the control signal S1 for controlling the on time of the transistor T104 is generated according to the delay time of the delay circuit D101.
However, since the timing of the switching of the level of the signal S1 is set by experience rather than after confirming the operational state of the band gap reference voltage circuit 20, it is not always set to the optimum value. If the switching time is too long, the start-up time of the voltage supply circuit becomes unnecessarily long and the start-up characteristic deteriorates, while if the switching time is too short, the start-up circuit stops before the voltage of the node n2 becomes sufficiently high which causes a possibility that the band gap reference circuit 20 will not start up normally.
Accordingly, careful attention is required when designing the start-up circuit. Further there are the drawbacks of susceptibility to manufacturing variance and variance in the operating conditions.